Quote
T. Hemperek, D. Arutinov, M. Barbero, R. Beccherle, G. Darbo, S. Dube, D. Elledge, D. Fougeron, M. Garcia-Sciveres, D. Gnani, V. Gromov, M. Karagounis, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni, J. D. Schipper, and N. Wermes, "Digital architecture of the new ATLAS pixel chip FE-I4," in 2009 IEEE Nuclear Science Symposium Conference Record, 2009, pp. 791-796.
Content
With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 ¿m2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.
References
DOI 10.1109/NSSMIC.2009.5402304
Keywords
Circuits
Clocks
Delay
Digital recording
Fires
Frequency
Large Hadron Collider
Memory
Nuclear and plasma sciences
Physics