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A new ATLAS pixel front-end IC for upgraded LHC luminosity

Journal article

Fast facts

  • Internal authorship

  • Further publishers

    M. Barbero, D. Arutinov, R. Beccherle, G. Darbo, R. Ely, D. Fougeron, M. Garcia-Sciveres, D. Gnani, T. Hemperek, R. Kluit, V. Kostioukhine, A. Mekkaoui, M. Menouni, J.-D. Schipper

  • Publishment

    • Elsevier (Amsterdam [u.a.]) 2009
  • Purpose of publication

  • Organizational unit

  • Subjects

    • General electrical engineering
  • Research fields

    • Other field of research

Quote

M. Barbero, D. Arutinov, R. Beccherle, G. Darbo, R. Ely, D. Fougeron, M. Garcia-Sciveres, D. Gnani, T. Hemperek, M. Karagounis, R. Kluit, V. Kostioukhine, A. Mekkaoui, M. Menouni, and J.-D. Schipper, "A new ATLAS pixel front-end IC for upgraded LHC luminosity," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 604, no. 1-2, pp. 397-399, 2009 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S0168900209002010

Content

A new pixel Front-End (FE) IC is being developed in a 130nm technology for use in the upgraded ATLAS pixel detector. The new pixel FE will be made of smaller pixels (50×250μm vs. 50×400μm for the present FE, FE-I3), a much improved active area over inactive area ratio, and a new analog pixel chain tuned for low power and new detector input capacitance. The higher luminosity for which this IC is tuned implies a complete redefinition of the digital architecture logic, which will not be based on End-of-Column data buffering but on local pixel logic and local pixel data storage. An overview of the new FE is given with particular emphasis on the new digital logic architecture and possible architecture variations.

References

Keywords

Digital architecture

FE-14

Pixel

Super-LHC

Notes and references

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