Zitat
V. Zivkovic, J. D. Schipper, R. Kluit, M. Garcia-Sciveres, A. Mekkaoui, M. Barbero, R. Beccherle, D. Gnani, T. Hemperek, M. Karagounis, M. Menouni, D. Fougeron, F. Gensolen, V. Gromov, A. Kruth, G. Darbo, J. FLEURY, J. C. Clemens, S. Dube, D. Elledge, A. Rozanov, and D. Arutinov, “The design for test architecture in digital section of the ATLAS FE-I4 chip,” Journal of Instrumentation, vol. 6, no. 01, p. C01090, 2011 [Online]. Available: https://doi.org/10.1088/1748-0221/6/01/C01090
Abstract
This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.
Referenzen
DOI 10.1088/1748-0221/6/01/C01090