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Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

Journal article

Fast facts

Internal authorship
Prof. Dr. Michael Karagounis
Further publishers
Marlon Barbero, David Arutinov, Roberto Beccherle, Giovanni Darbo, Sourabh Dube, David Elledge, Julien Fleury, Denis Fougeron, Maurice Garcia-Sciveres, Fabrice Gensolen, Dario Gnani, Vladimir Gromov, Frank Jensen, Tomasz Hemperek, Ruud Kluit, Andre Kruth, Abderrezak Mekkaoui, Mohsine Menouni, Jan David Schipper, Norbert Wermes, Vladimir Zivkovic
Publishment
- Elsevier (Amsterdam [u.a.]) 2011
Purpose of publication
Research
Organizational unit
Electrical engineering
Subjects
- General electrical engineering
Research fields
- Other field of research

Quote

M. Barbero, D. Arutinov, R. Beccherle, G. Darbo, S. Dube, D. Elledge, J. Fleury, D. Fougeron, M. Garcia-Sciveres, F. Gensolen, D. Gnani, V. Gromov, F. Jensen, T. Hemperek, M. Karagounis, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni, J. D. Schipper, N. Wermes, and V. Zivkovic, "Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 650, no. 1, pp. 111-114, 2011 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S0168900210026781

Content

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25μm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each 50×250μm2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A also contains various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.