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The FE-I4 pixel readout integrated circuit

Journal article

Fast facts

Internal authorship
Prof. Dr. Michael Karagounis
Further publishers
M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, D. Elledge, J. Fleury, D. Fougeron, F. Gensolen, D. Gnani, V. Gromov, T. Hemperek, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni, J.-D. Schipper
Publishment
- Elsevier (Amsterdam [u.a.]) 2011
Purpose of publication
Research
Organizational unit
Electrical engineering
Subjects
- General electrical engineering
Research fields
- Other field of research

Quote

M. Garcia-Sciveres, D. Arutinov, M. Barbero, R. Beccherle, S. Dube, D. Elledge, J. Fleury, D. Fougeron, F. Gensolen, D. Gnani, V. Gromov, T. Hemperek, M. Karagounis, R. Kluit, A. Kruth, A. Mekkaoui, M. Menouni, and J.-D. Schipper, "The FE-I4 pixel readout integrated circuit," Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 636, no. 1, Supplement, pp. 155-159, 2011 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S0168900210009551

Content

A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.