About the project
LearningChipsLab - Open Hardware Platform for Artificial Intelligence and Machine Learning
The need for resource efficient processors and application specific integrated circuits (ASIC) is growing for many applications in the field of Artificial Intelligence (AI) and Machine Learning (ML). Such applications cover condition monitoring, predictive maintenance, signal and sensor data analysis for big data, image and data processing. Many applications require cheap, energy efficient and compact embedded systems which can process their tasks autonomously or with a cloud/IoT connection. Furthermore, edge computing is of growing importance where signal processing power is moved as close as possible to the supervised system.
The Learning Chip Lab will develop technologies, methods and tools which support the design of resource efficient processor chips, so called application specific integrated circuits (ASIC), which are specifically adapted for ML and AI algorithms. The efficiency and high compactness of the rescource efficiency an integration of the chips into embedded systems which require a good energy efficiency, low cost, high robustness and high autonomy. For this goal, methods from electrical engineering, information technology and computer science will be combined. In detail, the lab will address the following topics with skills and research:
- Efficient processor and ASIC technologies which accelerate ML/AI algorithms while being resource efficient and implementation of such systems-on-chip (SoC) with leading edge, low power digital semiconductor technologies.
- Optimized ML/AI algorithms and accelerator architectures for the implementation into embedded processors and the integration with cloud and edge computing systems. A focus is put on time series analysis since there is a high relevance in industrial applications, e.g. smart building or smart energy systems.
- Open-source design tools for the model-based design of software and hardware solutions, as well as the integration of tool chains and design flows.
ASICs and the respective development methods are not sufficiently researched and available in this field, yet. Especially, small and midsize enterprises (SMEs) do not have a sufficient access to this technology. Therefore, the Learning Chips Lab will make all results accessible as Open Access/Open Source/Open Data, e.g. by using open chip architectures as RISC V and Open Source tools. The ramp-up of the Learning Chips Lab will be done based on the design of a pilot chip.
- Fachbereich Informationstechnik (Prof. Dr. Wöhrle)
- Fachbereich Elektrotechnik (Prof. Dr.-Ing. Karagounis)